Serial charge-redistribution cyclic digital-to-analog converters (CDACs) are generally known in the Background Art. Such a Background Art CDAC 700 is depicted in FIG. 7.
FIG. 7 is a schematic of a serial charge-redistribution cyclic digital-to-analog converter(CDAC) according to the Background Art.
Charge redistribution in CDAC 700 is achieved by selective control of MOS-type switches SB0-SB3 and SBINIT. Operation of CDAC 700 includes the following. Before beginning to convert an N-bit word, a charging capacitor CCH is initialized by discharging it via open switches SB1 and SB3 and a closed switch SB2 while a sharing capacitor CSH is initialized by discharging it via an open switches SB2 and SB3 and a closed switch SBINIT. Then, for each of the N bits in the word, a cycle of a charging mode followed by a sharing mode is iterated.
During the charging mode, the following occurs: charging capacitor CCH and a sharing capacitor CSH are isolated by an open switch SB2; according to the value of ith bit, di, capacitor CCH is charged to either VREF or VSS by a closed switch SB1 and an open switch SB0, or vice-versa, respectively; and a voltage on sharing capacitor CSH is maintained by open switches SB2, SB3 and SBINIT. During the subsequent sharing mode, the following occurs: charge on the charging capacitor CCH is shared with sharing capacitor CSH via open switches SB0 and SB1, a closed switch SB2 and open switches SB3 and SBINIT.
With each iteration, charge is permitted to accumulate on sharing capacitor CSH. After the charging/sharing cycle has been iterated for the Nth bit, the accumulated charge is provided to the non-inverting input of operational amplifier (op-amp) 702 via a closed switch SB3 and open switches SB2 and SBINIT.
As is known, distortion is introduced into the conversion by CDAC 700 due at least to two factors: (1) a capacitor mismatch error (e.g., due to manufacturing tolerances) between charging capacitor CCH and sharing capacitor CSH; and (2) a charge injection error caused by switch SB3.
Various attempts at reducing such distortions have been attempted. One such solution (not depicted) provides CDAC 700 with additional switches so that a swap can be made between alternative configurations for the charging capacitor CCH and the sharing capacitor CSH. More particularly, in a first configuration, a first capacitor C1 is connected as the charging capacitor CCH while a second capacitor C2 is connected as the sharing capacitor CSH. In a second configuration, the converse applies, namely the first capacitor C1 is connected as the sharing capacitor CSH and the second capacitor C2 is connected as the charging capacitor CCH. Without regard to the data words that are to be converted, an arbitrary choice is made for which the first or second configuration is used to begin the bit-by-bit conversion. The determination of whether to swap configurations for an ith bit is a cumulative calculation. Furthermore, the cumulative swap-decision calculation must be carried out in advance for all N bits because calculation proceeds from the most significant bit (MSB) to the least significant bit (LSB), whereas bit conversion itself typically proceeds from the LSB to the MSB.